1. Field of the Invention
The present invention relates to a thin film transistor, and a method for fabricating the same.
2. Background of the Related Art
Instead of a CMOS load transistor or a load resistor, a thin film transistor (hereinafter referred to as a TFT) may be used in an SRAM cell of 4M or more. The TFT may serve as a switching device that switches image data signals of a pixel region in a liquid crystal display device. In particular, a PMOS TFT may be used in an SRAM cell to reduce off-current and to increase on-current in a load resistor. Accordingly, the power consumption is diminished and memory characteristics are enhanced, thereby providing a high quality SRAM cell.
In such an SRAM cell, the correct formation and placement of offset regions of the TFTs with respect to other elements of the TFTs are important to the stability of the SRAM cell. Thus, the offset region must not be deformed or mis-aligned during the formation process.
A related art TFT and a method for fabricating the same will be described with reference to FIG. 1, which is a cross-sectional view showing a structure of the related art TFT. The TFT includes an insulating layer 21, a gate electrode 22a formed on a predetermined portion of the insulating layer 21, and a gate insulating film 24 formed on the insulating layer 21 and the gate electrode 22a. A drain electrode 25b is formed on the gate insulating film 24, spaced apart from the gate electrode 22a. A source electrode 25a is formed on the gate insulating film 24 such that it overlaps the gate electrode 22a. A channel region I and an offset region II are formed on the gate insulating film 24 between the source and drain electrodes 25a and 25b. In this case, the offset region II is placed between the drain electrode 25b and the gate electrode 22a.
A method for fabricating the related art TFT will now be described with reference to FIGS. 2A to 2D, which are cross-sectional views showing fabrication process steps of the related art TFT. As shown in FIG. 2A, a first polysilicon layer 22 for formation of a gate electrode of the TFT is formed on an insulating layer 21. A photoresist film is coated on the first polysilicon layer 22 and patterned with an exposure and development process to form a mask pattern 23.
Referring to FIG. 2B, the first polysilicon layer 22 is selectively removed by an etching process using the mask pattern 23, thereby forming a gate electrode 22a. A gate insulating film 24 is then deposited on the insulating layer 21 and the gate electrode 22a. Subsequently, a second polysilicon layer 25, which will be used as a source electrode, a drain electrode, an offset region, and a channel region, is formed on the gate insulating film 24. Next, a photoresist film 26 is coated on the second polysilicon layer 25.
Referring to FIG. 2C, the photoresist film 26 is patterned with an exposure and development process to mask the portion of the second polysilicon layer 25 that will become the channel and offset regions. With the photoresist pattern 26 serving as a mask, impurity ions are implanted in the exposed portions of the second polysilicon layer 25, thereby forming a source electrode 25a and a drain electrode 25b. Thereafter, the photoresist film 26 is removed. The source electrode 25a partially overlaps the gate electrode 22a, and the drain electrode 25b is spaced apart from the gate electrode 22a by a predetermined distance. A channel region I and an offset region II are formed between the source electrode 25a and the drain electrode 25b.
The related art TFT has several problems. First, processes using photoresist marks are necessary to form the offset and channel regions, the source electrode, and the drain electrode. The process used to create the photoresist masks can result in improper formation of the channel and offset regions due to misalignment of the photoresist. When this occurs, the reliability of a semiconductor device incorporating the TFT Is deteriorated. When this occurs during formation of an SRAM device, the stability of the cell can become negatively affected.